Using Reprogrammable Gate Arrays in Performance-Critical Designs

We describe our experiences with using reprogrammable gate arrays in performance-critical digital systems. Our experience indicates that RPGAs are easily integrated into the classroom, but are not yet sufficiently mature to permit comparable integration into a research environment. While reprogrammable gate arrays offer the potential for reduced area and chip count, routing and interconnect issues presently detract from their utility as building blocks in high-performance systems. We believe this is due to asymmetrical advancement rates of hardware and software technology. We point out the principal difficulties with using reprogrammable gate arrays in performance critical designs, and offer suggestions for improvement.